Integrated circuits are made up of millions of active devices formed in or on a substrate, such as a silicon wafer. The active devices are chemically and physically connected into a substrate and are interconnected through the use of multilevel interconnects to form functional circuits. Typical multilevel interconnects comprise a first metal layer, an interlevel dielectric layer, and sometimes a third and subsequent metal layers. Interlevel dielectrics, such as doped and undoped silicon dioxide (SiO2) and/or low-κ dielectrics, are used to electrically isolate the different metal layers. As each layer is formed, typically the layer is planarized to enable subsequent layers to be formed on top of the newly formed layer.
One way to fabricate planar metal circuit traces on a dielectric substrate is referred to as the damascene process. In accordance with this process, the dielectric surface is patterned by a conventional dry etch process to form holes and trenches for vertical and horizontal interconnects. The patterned surface is coated with an adhesion-promoting layer such as titanium or tantalum and/or a diffusion barrier layer such as titanium nitride or tantalum nitride. The adhesion-promoting layer and/or the diffusion barrier layer are then over-coated with a copper layer or a tungsten layer. Chemical-mechanical polishing is employed to reduce the thickness of the copper layer or tungsten over-layer, as well as the thickness of any adhesion-promoting layer and/or diffusion barrier layer, until a planar surface that exposes elevated portions of the silicon dioxide surface is obtained. The vias and trenches remain filled with electrically conductive copper or tungsten forming the circuit interconnects.
In some applications, it is desirable to employ an additional polishing step after polishing of a metal layer and/or a barrier layer in order to adequately planarize the dielectric surface. Typically, polishing compositions and methods suitable for the chemical-mechanical polishing of metal and/or barrier layers are not suitable for the polishing of dielectric layers comprising silicon dioxide.
Another semiconductor fabrication method requiring the polishing of silicon dioxide layers is the shallow trench isolation (STI) process. In accordance with the STI process, a silicon nitride layer is formed on a silicon substrate, shallow trenches are formed via etching or photolithography, and a dielectric layer, typically silicon dioxide, is deposited to fill the trenches. Due to variation in the depth of trenches formed in this manner, it is typically necessary to deposit an excess of dielectric material on top of the substrate to ensure complete filling of all trenches.
The dielectric material conforms to the underlying topography of the substrate. Thus, the surface of the substrate is characterized by raised areas of the overlying oxide between trenches. The excess dielectric lying outside of the trenches is then typically removed by a chemical-mechanical planarization process, which additionally provides a planar surface for further processing.
Currently, there are two primary methods used in the chemical-mechanical planarization of silicon dioxide. A first method comprises use of high solids content (10-20 wt. %) silica-based polishing compositions having a pH of greater than 10. The high solids content results in a high cost for such polishing compositions. A second method comprises use of cerium oxide abrasives in polishing compositions. Although cerium oxide-based polishing compositions exhibit high removal rates when used to polish silicon dioxide layers, cerium ions derived from the cerium oxide abrasive can contaminate substrate structures, necessitating aggressive post-CMP cleaning processes. Disadvantages of these polishing compositions include low polishing rates when the silica content is reduced, higher costs when the silica content is increased to raise the polishing rates, and low polishing rates typically exhibited with respect to other components of the substrate surface, such as tantalum.
Thus, there remains a need in the art for compositions and methods for chemical-mechanical planarization of silicon dioxide-containing substrates that will provide useful removal rates for silicon dioxide.